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RISC-V Architecture Reaches 10 Billion Cores Shipped

Calista Redmond, CEO of RISC-V Internationalannounced at Embedded World that there are currently ten billion RISC-V cores on the marketwhich marks a milestone for the company and an architecture postulated as a strong competitor to the x86 and ARM architectures.

Calista said open standards are key: “Linux does it for software and we do it for hardware. We estimate there are 10 billion RISC-V cores in the market.”


As a reference, the ARM architecture took 17 years to reach this milestone in 2008, while RISC-V “only” took about 12 years old.

The director also revealed that the number of commercially available RISC-V processor cores is expected to reach a figure of 80 billion in 2025. In other words, it took more than 12 years to reach the 10,000 million mark, and now in 3 years they expect a boom that adds 70,000 million additional RISC-V cores on the market.

On June 21, RISC-V International also announced the approval of the first four specifications and extensions by 2022: Efficient Trace (E-trace), Supervisor Binary Interface (SBI), Unified Extensible Firmware Interface (UEFI) and the Zmmul pure multiplication extension.

  • E-trace defines a very efficient approach to processor tracing that uses branch tracing, ideal for debugging any type of application, from small embedded designs to super powerful computers. The E-Trace documentation for RISC-V specifies the signals between the RISC-V core and the encoder (or input port), a compressed branch tracing algorithm, and a packet format to encapsulate the trace information. compressed branch. . The development and ratification of this specification was led by Gajinder Panesar of Picocom and the RISC-V E-Trace working group.

“RISC-V SBI offers developers an equally essential resource,” Himelstein added. “The ability to port software in supervisor mode to all RISC-V implementations, essentially allowing developers to write something once and apply it everywhere.”

  • The SBI specification establishes a firmware layer between the hardware platform and the operating system kernel through an application binary interface in supervisor mode (S or VS mode). This abstraction enables platform services common to all RISC-V operating system implementations. Many RISC-V members have already implemented the RISC-V SBI specification in their RISC-V solutions, so ratifying the specification will ensure a standard approach across the entire RISC-V ecosystem, ensuring compatibility. The development and ratification of this specification was led by Atish Patra de Rivos, with work carried out within the Platform’s Horizontal Steering Committee.

“UEFI is an essential part of any system,” Himelstein said, “in some applications it can replace basic BIOS software.”

  • UEFI Protocols they bring existing UEFI standards to RISC-V platforms. The development and ratification of this specification was led by Sunil VL of Ventana Micro and Philipp Tomsich of VRULL GmbH, with work done within the Privileged Software Technical Working Group.

“For many microcontroller applications, splitting operations are too infrequent to justify the cost of splitting hardware,” Himelstein explained. “The RISC-V Zmmul extension will particularly benefit simple FPGA soft cores.”

  • Zmmul Multiply only it allows low-cost implementations that require multiply but not divide operations and is part of the RISC-V Unprivileged specification. The development and ratification of this extension was led by Allen Baum, with work done within the ISA Non-Privileged Committee.

via: MyDrivers

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