The future is already written and we are on our way to it. We need to move away from FinFET transistors and fully embrace GAA, but at the same time we need to create new lithographic processes made with newer technologies. The first step is to go to the fries with the call EUV High NAbut although the technology is nearing completion, ASML showed the difficulties that the two TSMC (AMD and NVIDIA) What Intel to create the new bullets and how it was fixed.
The changes are substantial, the challenge is impressive and we are talking about the most advanced technology in the world, no one even comes close, it is the best of the best on a planetary level and everything, as always happens in these cases, goes to the optics of ASML scanners.
The problem of chips with EUV High-NA vs. “Traditional” EUV
Surely we know that a chip, be it CPU or GPU, APU or similar, is created with several layers and with several masks, where these are registered by means of a extreme ultraviolet (EUV) laser light beam. Reducing the etch capacity to be able to create smaller transistors in the same space is key for all current and past chips, but it faces challenges and in the case of EUV more.
As we were able to find out on our own ASMLeach etching mask for EUV has a series of MoSI or monosilicon multilayers which, when traversed by the ultraviolet light beam, exhibit a series of reflectionsreflections so that we understand each other, so reaching the last layer is very complicated and if the chip has too much of it it makes it impossible.
EUV performs a 60% average in terms of reflections, which are magnified or reduced depending on how many degrees the laser incises against the mask and wafer. As we know for sure, EUV operates at a wavelength of 0.33NAgood of 11 degrees the reflections are of such a caliber that they make etching impossible and therefore this is the limit of this technology and with said wavelength.
So what happens to this technology and its 0.55?
Well here is the magic that future chips from Intel, NVIDIA and AMD (among others) will have, since ASML has pulled out of the hat a solution as simple to understand as it is difficult to implement: an anamorphic lens.
To achieve a wavelength of 0.55NAwhere this lens opening is only possible if the mask and the wafer are incised at an angle of 18º, which does not allow precision as such. So the problem is that you have to focus below 10thso that the new anamorphic lens manages to maintain a separation between the beams of 8º while one of them remains in 9thwhich improves the reflection for each engraving.
Now that you want to produce as many wafers per hour as possible, you need to increase the speed of the wafer and mask step.
Imagine the precession of this movement projecting 188 half-fields per wafer and 220 wafers per hour. pic.twitter.com/FjI7no54iy
—Andreas Schilling 🇺🇦 (@aschiling) June 17, 2022
The problem, logically, is that once such an anamorphic lens has been created (of which nothing more is known) it is that recording with more precision requires more time and logically fewer wafers per hour are produced .
Two different concepts come into play here: Half field and full field, which refer to the average size of a chip in mm2 in the case of the first (350mm2), while the second returns the full die size on the surface, i.e. the maximum die size that could be created (850mm2).
The performance of a scanner is measured in WPH, i.e. in wafers per hour (not to be confused with chips per hour) where with EUV High-NA we would have 220a lower number for now than with EUV, so as a result the chips will be more expensive if you add in the complexity of etching, the lower performance and also the price of each scanner (+-400 million dollars).
The good thing about this is that we have managed to break down the first barrier to the sustainable reduction of lithography, we will see when we come down from the atom what steps ASML has to take and with what technology it surprises us.